ALU

Contenuto del file

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.ALL;

entity simple_alu is
port(   a,b : in std_logic_vector(7 downto 0); --input operands
        op : in std_logic_vector(2 downto 0); --Operation to be performed
        r : out std_logic_vector(7 downto 0);  --output of ALU
        zero,sign: out std_logic);
end simple_alu;

architecture behav of simple_alu is

begin

process(a,b,op)
variable op1,op2,result : signed(7 downto 0) := (others => '0');
begin

        op1:=signed(a); 
        op2:=signed(b); 
        case op is
            when "000" => result := op1 + "00000001";
            when "001" => result := op1 + op2;
            when "010" => result := op1 - op2;
            when "011" => result := not op1;
            when "100" => result := op1 and op2;
            when "101" => result := op1 or op2;
            when "110" => result := op1 xor op2;
            when "111" => result := "00000000";
            when others => NULL;
        end case;

        r <= std_logic_vector(result);

        if (result=0) then
          zero<='1';
        else
          zero<='0';
        end if;
        if (result<0) then
          sign<='1';
        else
          sign<='0';
        end if;

end process;

end behav;