algoritmo gcd

Contenuto del file

-- high-level description of a gcd evaluator, no timing, description
-- non directly synthesizable
library IEEE;
use IEEE.STD_LOGIC_1164.all,ieee.numeric_std.all;

entity gcd is
	 port(
		 a : in STD_LOGIC_VECTOR(7 downto 0);
		 b : in STD_LOGIC_VECTOR(7 downto 0);
		 gcd : out STD_LOGIC_VECTOR(7 downto 0)
	     );
end gcd;

architecture behav of gcd is
begin

	process(a,b)
	variable vara,varb: unsigned(7 downto 0);
	constant zero: std_logic_vector(7 downto 0):=(others=>'0');
	begin
		if (a=zero) or (b=zero) or (is_x(a)) or (is_x(b)) then
		  gcd <= (others=>'X');
		else
			vara:=unsigned(a);
			varb:=unsigned(b);
			while (vara/=varb) loop
				if (vara<varb) then
					varb:=varb-vara;
				else
					vara:=vara-varb;
				end if;
			end loop;
			gcd <= std_logic_vector(vara);
		end if;
	end process;
end architecture behav;